Charted: The Real AI GPU Bottleneck — HBM Memory & CoWoS Packaging, Not 3nm Fabs
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The bottleneck moved downstream
Headlines still obsess over 3nm and 2nm wafer capacity at TSMC and Samsung. But in 2025 the binding constraint on AI accelerator shipments shifted to two packaging layers: High Bandwidth Memory (HBM) stacked beside the GPU die, and CoWoS (Chip-on-Wafer-on-Substrate) — the only production-proven 2.5D integration technology that wires them together.
TSMC Chairman C.C. Wei said CoWoS was sold out through 2025 and into 2026. Every NVIDIA Blackwell, AMD MI300, and Google TPU needs both a CoWoS slot and an HBM allocation. Without both, a finished AI GPU cannot ship — no matter how many front-end wafers exist.
The interactive chart above tracks 27 sourced supply-chain records across HBM vendors, CoWoS capacity, customer allocations, and OSAT outsourcing.
HBM: a $46.7B market sold out
TrendForce projects the global HBM market reaches $46.7 billion in 2025 — up 156% from $18.2B in 2024. HBM will account for 34% of total DRAM revenue and 85% of HBM shipments will be HBM3E, driven by NVIDIA Blackwell.
The supplier hierarchy is stark:
- **SK hynix52.3%** HBM market share (TrendForce, Aug 2025); sold out for 2025, taking 2026 orders
- **Samsung28.7%**; down from 41% as 12-hi HBM3E NVIDIA verification lagged
- **Micron19.0%**; ramping Idaho and Malaysia lines toward 20–25% share
NVIDIA alone drove an estimated 27% of SK hynix total revenue in 1H25 — more than any other customer in the company's history. BofA forecasts HBM TAM reaches $54.6B in 2026 (+58% YoY).
CoWoS: capacity doubles, demand triples
TSMC expanded CoWoS from roughly 37,500 wpm at end-2024 to a target of 75,000 wpm by end-2025 — nearly doubling output via AP8 (ex-Innolux) and Taichung lines. The 2026 target: 120,000–130,000 wpm.
Yet demand outruns supply:
| Year | CoWoS demand | TSMC capacity (annualized) |
|---|---|---|
| 2024 | ~370K wafers | ~450K wafers |
| 2025 | ~670K wafers | ~900K wafers |
| 2026 | ~1.0M wafers | ~1.5M wafers (target) |
Even at the 2026 capacity target, lines stay fully booked with 52–78 week lead times. Capacity growth ≠ availability when demand grows faster.
Who gets the slots?
NVIDIA dominates allocation: an estimated 400,000 CoWoS wafers in 2025 (~60% of TSMC output), rising to 700,000 in 2026 as Blackwell Ultra and Vera Rubin ramp. The remainder is split among AMD (~55K), Google (~80K rising to 240K target), Broadcom custom ASICs (~40K), and Marvell.
Google's TPU v7 push illustrates the squeeze: target demand of 240,000 wafers in 2026, but GlobalSemiResearch estimates TSMC can deliver only 150,000–180,000 — enough for ~3.2M TPUs against a ~6M unit goal.
OSAT: TSMC's relief valve
TSMC is outsourcing a growing share of CoWoS workload to OSAT partners:
- **Amkor180,000–190,000 wafers/yr** (2026), Arizona and Vietnam
- **SPIL/ASE60,000–80,000 wafers/yr** (2026), Taiwan
- **Combined OSAT240,000–270,000 wafers/yr**
NVIDIA reportedly outsources 50% of CoWoS in 2025 and 70–80% in 2026 as CoWoS-L complexity rises. OSAT is not a full substitute — TSMC retains CoWoS-L with silicon bridge interposers — but it relieves CoWoS-S substrate bottlenecks.
Why this is not a fab problem
Leading-edge N2 and A16 nodes at TSMC are also tight, but the queue mechanics differ. Fab capacity expands on predictable cadences; CoWoS requires specialized cleanroom bays, interposer fabs, and substrate supply chains that cannot be cloned in 12 months. HBM needs TSV drilling, stacking, and logic-die proximity that conventional DRAM lines cannot produce.
The compound constraint: a single B200 module needs ~192GB HBM3E (8 stacks × 24GB) and a CoWoS-L package and a reticle-limited 4NP logic die. Missing any one component zeros the shipment.
What to watch in 2025–2026
- HBM4 qualification for NVIDIA Vera RubinSK hynix and Samsung both qualified by mid-2026
- CoWoS-L to CoPoS transitionTSMC's next-gen panel-level packaging for 2027+
- Amkor Arizona rampfirst major US advanced-packaging volume for AI chips
- Samsung HBM recoverywhether 12-hi HBM3E share recovers or Micron takes slot 3 permanently
- Custom ASIC HBM demandGoldman projects +82% YoY for ASIC-attached HBM, diversifying beyond NVIDIA
- CoWoS pricingpackaging BOM reportedly +20% on AI accelerator builds in 2026
Methodology
Supply-chain records compiled from TrendForce (HBM market sizing, supplier share, CoWoS capacity), TSMC investor disclosures (C.C. Wei, Jun He), SK hynix investor materials, Silicon Analysts CoWoS capacity tracker, and GlobalSemiResearch customer allocation estimates. Primary data year 2025; 2026 figures are publicly sourced forecasts and capacity targets, not realized output. CoWoS capacity in wafer starts per month (wpm); annual demand in wafers per year. HBM market share figures are TrendForce revenue-based estimates (Aug 2025). OSAT outsourcing figures trace to GlobalSemiResearch sell-side models — medium confidence, single-source. This dataset tracks the packaging/memory bottleneck specifically; it does not include leading-edge fab utilization or substrate (ABF) supply, which are separate constraints.